| Display title | Engineering:Transmeta Efficeon |
| Default sort key | Transmeta Efficeon |
| Page length (in bytes) | 3,960 |
| Namespace ID | 3034 |
| Namespace | Engineering |
| Page ID | 37865 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Page image |  |
| HandWiki item ID | None |
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
| Page creator | imported>Nautica |
| Date of page creation | 20:37, 3 February 2024 |
| Latest editor | imported>Nautica |
| Date of latest edit | 20:37, 3 February 2024 |
| Total number of edits | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Description | Content |
Article description: (description)
This attribute controls the content of the description and og:description elements. | The Efficeon (stylized as efficēon) processor is Transmeta's second-generation 256-bit VLIW design released in 2004 which employs a software engine Code Morphing Software (CMS) to convert code written for x86 processors to the native instruction set of the chip. Like its predecessor, the Transmeta Crusoe... |
