| Display title | Engineering:Compute Express Link |
| Default sort key | Compute Express Link |
| Page length (in bytes) | 21,360 |
| Namespace ID | 3034 |
| Namespace | Engineering |
| Page ID | 576559 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| HandWiki item ID | None |
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
| Page creator | imported>SpringEdit |
| Date of page creation | 23:04, 3 February 2024 |
| Latest editor | imported>SpringEdit |
| Date of latest edit | 23:04, 3 February 2024 |
| Total number of edits | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Description | Content |
Article description: (description)
This attribute controls the content of the description and og:description elements. | Compute Express Link (CXL) is an open standard for high-speed, high capacity central processing unit (CPU)-to-device and CPU-to-memory connections, designed for high performance data center computers. CXL is built on the serial PCI Express (PCIe) physical and electrical interface and includes PCIe-based... |
