| Display title | Engineering:10 nm process |
| Default sort key | 10 nanometre |
| Page length (in bytes) | 24,678 |
| Namespace ID | 3034 |
| Namespace | Engineering |
| Page ID | 602410 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| HandWiki item ID | None |
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
| Page creator | imported>Smart bot editor |
| Date of page creation | 12:54, 25 June 2023 |
| Latest editor | imported>Smart bot editor |
| Date of latest edit | 12:54, 25 June 2023 |
| Total number of edits | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Description | Content |
Article description: (description)
This attribute controls the content of the description and og:description elements. | In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFET technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nm.
All production "10 ... |
